What exactly is an ARM processor?
The Advanced RISC Machine and the Acorn RISC Machine were two prior names for the 32-bit reduced instruction set (RISC) processor architecture known as the ARM architecture. Because of its low power consumption and high energy efficiency, the ARM processor is commonly used in embedded system architecture. This makes it perfect for mobile communication. Consumer electronics includes portable devices like PDAs, mobile phones, multimedia players, handheld computers, and handheld electronic games as well as computer peripherals like hard drives and desktop routers as well as even military hardware like missile onboard computers. More details you can visit easybom.
Application area and ARM microprocessor characteristics
The ARM processor has the greatest market penetration and the broadest development trend. Currently, 80% of the market is occupied by 32-bit processors built on the ARM architecture. The majority of IC producers have introduced their own ARM chips.
Industrial control field: ARM core-based microcontroller chips, which have a 32 RISC architecture, not only account for the majority of the high-end microcontroller market share, but are also progressively making inroads into the low-end microcontroller application space. The traditional 8-bit / 16-bit microcontroller is challenged by the high cost performance and low power consumption of ARM microcontroller.
Due to its great performance and low cost, ARM technology is currently used in more than 85% of wireless communication devices. As a result, ARM is steadily strengthening its dominance in this market.
Equipment for networks: ADSL chips utilizing ARM technology are gradually obtaining competitive benefits as broadband technology is promoted. The application field of DSP is also challenged by the fact that ARM has been widely adopted and has been optimized for speech and video processing.
Consumer electronics: Popular digital audio players, digital set-top boxes, and gaming consoles all employ ARM technology.
Products for imaging and security: Most widely used digital cameras and printers employ ARM technology. Additionally using ARM technology is the phone’s 32-bit SIM smart card.
What an ARM processor has:
- Compact size, low power usage, low price, and good performance;
- Support the dual instruction set of Thumb (16 bit) and ARM (32 bit), which makes it very compatible with 8 bit and 16 bit devices;
- A lot of registers, higher speed of instruction execution;
- Registers are where most data operations are carried out;
- The way of addressing is adaptable and straightforward, highly effective;
- The length of the instruction is fixed;
Several crucial ideas regarding the ARM
Von Neumann system
Features of the von Neumann system
- Instruction and data fetching use the same data channel, and data and instructions are stored in the same storage region. most early computers made use of.
- Von Neumann architecture on the ARM7 is straightforward yet sluggish. Data cannot be fetched simultaneously, which is indicated by the term fetching.
System of Harvard
- Organize your program and data memory separately.
- Offers a lot of memory bandwidth, and each has an own bus.
- Appropriate for handling digital signals.
- Harvard designs make up the majority of DSPS.
A Harvard architecture is ARM9. Three stores make up the Harvard architecture: program, data, program, and data sharing.
Computerized Instruction Set
- With several different addressing modes and instructions
- The 80%/20% rule states that only 80% of instructions are used by programs.
- The majority of programs can be executed with just a few instructions.
- Because CISC CPUs include a big number of cell circuits, they are powerful, take up a lot of space, and use a lot of power.
Computer with Limited Instruction Set (RISC)
- Only provide the simplest actions in the channel, and only include the most helpful instructions.
- Ensure that each command is quickly carried out via the data channel.
- Loading-storing Only the data in registers are processed by the processor. Data is transferred between registers and external storage via load-store instructions.
- Reduce the number of unit circuits in RISC CPUs, which results in a smaller form factor and lower power consumption.
Principal distinctions between RISC and CISC
More general-purpose registers, each of which may store data and addresses, are present in the RISC instruction set. All data operations can quickly access storage through registers.
CISC instruction set: A unique register mostly used for a single function.
- Load-store architecture
RISC architecture: The CPU only processes the information in the register; the data transfer between the register and external memory is carried out by a separate, specialized load-store instruction. (Access takes time; processing and storage are separate; data saved in the register can be used repeatedly; thus prevents frequent access to the external memory.)
CISC architecture: Capable of processing memory-based data directly.
Storage format for ARM
Each storage unit in ARM storage is given a storage address and used to store data in 8-bit (or one byte) chunks.
Memory is seen by ARM as a linear collection of bytes beginning at address zero. The MAXIMUM addressing area enabled by the ARM architecture as a 32-bit microprocessor is 4GB (232 bytes). The first stored word data is arranged from 0 to 3 bytes, while the second stored word data is arranged in sequence from 4 to 7 bytes. Two address cells are used for 16-bit half data while four are used for 32-bit word data. Consequently, there is a difficulty with the stored word or half-word data’s ordering. The big-endian and little-endian formats are two ways that the ARM architecture can store word data.
Big-endian format stores word data in low addresses for high-byte words and high addresses for low-byte words.
The opposite of big-endian is low-endian. The low address keeps track of the word data’s low bytes, while the high address keeps track of its high bytes. The small endian setting is the default.
ARM product series
ARM processor classification
Instruction set architecture-based classification: V1, V2, V5, v5TEJ, v6, etc.
Classification of processors depending on their kernels: ARM7, ARM9, ARM10, ARM11, StrongARM, XScale, etc.
Version of ARM architecture
Since its inception, ARM architecture has seen significant development. Versions defined thus far include V1, V2, V3, V4, V5, and V6.
Version 1 of the architectural design
The essential characteristics of this architecture, which was only visible in the ARM1 prototype, are as follows:
- Basic guidelines for data processing (no multiplication)
- Instructions for loading and storing bytes, half-words, and words
- Instructions for linking and calling subroutines are all transfer instructions.
- Software interrupt command
5.64M of addressing space (26)
Version 2 of the architectural design
The following characteristics add to version V1, or the ARM2 architecture, in this architecture version:
1, Instructions + multiplication and multiplication
- Instructions for operating a support coprocessor
- Quick interruption mode
- Basic memory and register exchange instruction for SWP/SWPB
5, 64M of addressing space
Version 3 of the architecture
- The addressing space should be increased to 32 bits (4G bytes),
- To speed up the processing of exceptions, the current program state register CPSR and program state saving register SPSR are added.
- Abort and undefined processor modes have been added.
- It is the architecture of ARM6.
- The ability to return instructions from exception handling was added, and MRS/MSR instructions were provided to access the newly added CPSR/SPSR registers.
Version 4 of the architecture
The 16-bit Thumb instruction set was released and the V3 version architecture has been further enlarged, making the V4 version architecture the most popular ARM architecture at the moment. This architecture is used by the ARM7, ARM8, and StrongARM processors.
The instruction set now includes the following extra features:
- Instructions for loading and storing signed bytes, signed halfwords, and signed bytes.
- 16-bit Thumb instruction set added
- Enhanced software interrupt SWI instruction performance
- A processor privileging mode was added.
Version 5 of the architecture
This is the ARM architecture that was just released, and the V4 version basically introduced some new instructions. This version of the architecture uses ARM10 and XScale, and the new instructions are:
- Linking and exchanging BLX instructions will transfer
- CLZ opcode for count leading zero
- Software breakpoint directive
- further guidelines for signal processing
Boost the coprocessor’s optional instruction count.
Version 6 of the architecture
- Appropriate for use with battery-operated portable equipment
- To increase the embedded application system’s ability to process audio and video, a SIMD function extension was included.
General guidelines for choosing ARM chips
The following are the primary application-related criteria to take into account while selecting ARM chips:
ARM core: You must use ARM chips with MMU function over ARM720T if you wish to use WinCE, Linux, or other operating systems to speed up software development.
System clock controller: The system clock controls how quickly an ARM chip processes information. The ARM7 chip operates at a 0.9MIPS/MHz processing rate. The processing speed of the ARM9 chip is 1.1MIPS/MHz, while the primary clock of the COMMON ARM7 chip spans from 20 MIPS to 133MHz. The typical ARM9 chip’s primary clock frequency spans from 100 MIPS to 233MHz.
Internal memory capacity: ARM chips with built-in memory might be taken into consideration when huge capacity memory is not required.
GPIO amount: The maximum GPIO quantity is frequently indicated in the instructions provided by some chip makers, but many pins are multiplexed with address lines, data lines, serial lines, and other pins. This means that during system design, it is necessary to determine the real number of GPIO that can be used.
USB interface: Many ARM processors come equipped with a USB controller that can function as both a USB host and a USB slave.
Interrupt controller: The only interrupt vectors supported by the ARM kernel are the fast interrupt (FIQ) and standard interrupt (IRQ) vectors. However, when developing processors to handle hardware interrupts like serial ports, external interrupts, and clock interrupts, many semiconductor manufacturers incorporate their own interrupt controllers. The choice of a chip must take external interrupt control into account. The workload of task scheduling can be significantly reduced by a reasonable external interrupt design.
LCD controller: Some ARM chips are equipped with an LCD controller; a few of them even have a 64K color TFT LCD controller. The selection of an ARM chip with an integrated LCD controller is more appropriate for creating PDA and handheld display and recording devices.
Expansion bus: The majority of ARM chips offer ports for external SDRAM and SRAM expansion. The number of chips, or the number of selected lines, that can be increased by various ARM chips varies. Some specialized ARM chips, such the PUC3030A from German Micronas, lack an external extension function.
Packaging: There are several different types of packaging, including QFP, TQFP, PQFP, LQFP, BGA, and LBGA. BGA packaging has the advantage of having a small chip area, which can minimize the size of the PCB board, but it also necessitates specialized welding equipment and cannot be manually welded. Additionally, multi-layer PCB wiring is necessary for general BGA packed ARM chips because double panels cannot finish PCB wiring for these chips.
Using a thumb device
Low power, small volume, and high performance solutions have been made possible by the introduction of RISC architecture for ARM. The ARM architecture adds the T variant and creates a new instruction set, the Thumb instruction set, which is a key component of ARM technology, to address the issue of code length.
The ARM architecture is expanded by Thumb. It features 36 instruction formats that were taken from the common 32-bit ARM instruction set and converted to 16-bit opcodes. High coding density results as a result.
It is simple to run in the Thumb state, where the instruction set is a 16-bit Thumb instruction set, in the processor state of the ARM architecture that supports Thumb.
This can be compared to the ARM instruction set. The following restrictions apply to the Thumb instruction set:
- The ARM instruction set is more suited for applications with stringent restrictions on system running time than thumb instructions, which typically take more instructions to perform the same action.
- In the event of an exception interruption, ARM instructions are still required because the Thumb instruction set lacks some instructions required for exception handling. Because of this restriction, ARM instruction and Thumb instruction must be combined.
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